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features ? supply voltage 5v very low power consumption 125 mw very good image rejection by means of phase control loop for precise 90 phase shifting duty-cycle regeneration for single-ended lo input signal low lo input level ?10 dbm lo frequency from 70 mhz to 1 ghz power-down mode 25 db gain control very low i/q output dc offset voltage typically < 5 mv benefits low current consumption easy to implement perfect performance for large variety of wireless applications electrostatic sensitive device. observe precautions for handling. 1. description the silicon monolithic integr ated circuit u2794b is a quadrature dem odulator manu- factured using atmel?s advanced uhf technology. this demodulator features a frequency range from 70 mhz to 1000 mhz, low current consumption, selectable gain, power-down mode and adjustment-free handling. the ic is suitable for direct conver- sion and image rejection applications in di gital radio systems up to 1 ghz such as cellular radios, cordless telephones, cable tv and satellite tv systems. 1000-mhz quadrature demodulator u2794b rev. 4653d?cell?11/05
2 4653d?cell?11/05 u2794b figure 1-1. block diagram 2. pin configuration figure 2-1. pinning sso20 90control loop 90 0 frequency doubler duty cycle regenerator power down 14 5,6 v s pu 4 3 17 1 2 19 20 10 9 16,18 11 gc gnd 7 8 rf in iix ii output ix i lo 12 13 pc pcx output q qx qq qqx 15 1 2 3 4 5 6 7 8 10 9 19 18 17 16 14 15 13 12 11 20 ix i ii v s v s qq qqx iix qx q gnd lo in gnd pu pc pcx gc rf in rfx in lox in
3 4653d?cell?11/05 u2794b table 2-1. pin description pin symbol function 1ixix output 2 i i output 3 ii ii lowpass filter i 4 iix iix lowpass filter i 5v s supply voltage 6v s supply voltage 7rf in rf input 8rfx in rfx input 9 qq qq lowpass filter q 10 qqx qqx lowpass filter q 11 gc gc gain control 12 pcx pcx phase control 13 pc pc phase control 14 pu pu power up 15 lox in lox input 16 gnd ground 17 lo in lo input 18 gnd ground 19 q q output 20 qx qx output
4 4653d?cell?11/05 u2794b 3. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol value unit supply voltage v s 6v input voltage v i 0 to v s v junction temperature t j +125 c storage-temperature range t stg ?40 to +125 c 4. thermal resistance parameters symbol value unit junction ambient sso20 r thja 140 k/w 5. operating range parameters symbol value unit supply-voltage range v s 4.75 to 5.25 v ambient-temperature range t amb ?40 to +85 c
5 4653d?cell?11/05 u2794b 6. electrical characteristics test conditions (unless otherwise specified); v s = 5v, t amb = 25c, referred to test circuit system impedance z o = 50 ? , f ilo = 950 mhz, p ilo = ?10 dbm no. parameters test conditions pin symbol min. typ. max. unit type* 1.1 supply-voltage range 5, 6 v s 4.75 5.25 v a 1.2 supply current 5, 6 i s 22 30 35 ma a 2 power-down mode 2.1 ?off? mode supply current v pu 0.5v v pu = 1.0 v (1) 14, 5 6 i spu 1 20 a a b d 3switch voltage 3.1 ?power on? 14 v pon 4vd 3.2 ?power down? 14 v poff 1vd 4 lo input, lo in 4.1 frequency range 17 f ilo 70 1000 mhz d 4.2 input level (2) 17 p ilo ?12 ?10 ?5 dbm d 4.3 input impedance see figure 6-10 17 z ilo 50 ? d 4.4 voltage standing wave ratio see figure 6-3 17 vswr lo 1.2 2 d 4.5 duty-cycle range 17 dcr lo 0.4 0.6 d 5 rf input, rf in 5.1 noise figure (dsb) symmetrical output at 950 mhz (3) at 100 mhz 7, 8 nf 12 10 db d 5.2 frequency range f irf = f ilo bw yq 7, 8 f irf 40 1030 mhz d 5.3 ?1 db input compression point high gain low gain 7, 8 p 1dbhg p 1dblg ?8 +3.5 dbm d 5.4 second order iip (4) 7, 8 iip 2hg 35 dbm d 5.5 third order iip high gain low gain 7, 8 iip 3hg iip 3lg +3 +13 dbm d 5.6 lo leakage symmetric input asymmetric input 7, 8 l ol ?60 ?55 dbm d 5.7 input impedance see figure 6-10 7, 8 z irf 500ii0.8 ? iipf d *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter notes: 1. during power-down status a load circuitry with dc- isolation to gnd is assumed, otherwise a current of i (vs ?0.8v)/ri has to be added to the above power-down current for each output i, ix, q, qx. 2. the required lo-level is a func tion of the lo frequency (see figure 6-6 ). 3. measured with input matching. for 950 mhz, the optional transmission line t3 at the rf input may be used for this pur- pose. noise figure measurements without using the diff erential output signal result in a worse noise figure. 4. using pins 7 and 8 as a symmetric rf in put, the second-order iip can be improved. 5. due to test board parasitics, this bandwidth may be reduced and not be equal for i, ix, q, qx. if symmetry and full band- width is required, the lowpass pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the i/q outputs can be increased further by using a resistor between pins 3, 4, 9 and 10. these resistors shunt the internal loads of ri ~ 5.4 k ? . the decrease in gain here has to be considered. 6. the internal current of the output emitter followers is 0.6 ma. this redu ces the undistorted output voltage swing at a 50 ? load to approximately 30 mv. for low signal distortion the load impedance should be ri 5 k ? . 7. referred to the level of the output vector 8. the low-gain status is achieved with an open or high- ohmic pin 11. a recommended application circuit for switching between high and low gain status is shown in figure 6-1 . i 2 q 2 +
6 4653d?cell?11/05 u2794b 6 i/q outputs (i, ix, q, qx) emitter follower i = 0.6 ma 6.1 3-db bandwidth w/o external c 1, 2, 19, 20 bwi/q 30 mhz d 6.2 i/q amplitude error 1, 2, 19, 20 ae ?0.5 0.2 +0.5 db b 6.3 i/q phase error 1, 2, 19, 20 pe ?3 1.5 +3 deg b 6.4 i/q maximum output swing symm. output r l > 5 k ? 1, 2, 19, 20 v pp 2d 6.5 dc output voltage 1, 2, 19, 20 v out 2.5 2.8 3.1 v a 6.6 dc output offset voltage (6) 1, 2, 19, 20 v offset < 5 mv te s t spec. 6.7 output impedance see figure 6-10 1, 2, 19, 20 z out 50 ? d 7 gain control, gc 7.1 control range power gain high gain low (7) 11 gcr g h g l 25 23 ?2 db dbm dbm d b d 7.2 switch voltage 7.3 ?gain high? 11 1 v 7.4 ?gain low? (8) 11 < open 7.5 settling time, st 7.6 power ?off? - ?on? t son < 4 s d 7.7 power ?on? - ?off? t soff < 4 s d 6. electrical characteristics (continued) test conditions (unless otherwise specified); v s = 5v, t amb = 25c, referred to test circuit system impedance z o = 50 ? , f ilo = 950 mhz, p ilo = ?10 dbm no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter notes: 1. during power-down status a load circuitry with dc- isolation to gnd is assumed, otherwise a current of i (vs ?0.8v)/ri has to be added to the above power-down current for each output i, ix, q, qx. 2. the required lo-level is a func tion of the lo frequency (see figure 6-6 ). 3. measured with input matching. for 950 mhz, the optional transmission line t3 at the rf input may be used for this pur- pose. noise figure measurements without using the diff erential output signal result in a worse noise figure. 4. using pins 7 and 8 as a symmetric rf in put, the second-order iip can be improved. 5. due to test board parasitics, this bandwidth may be reduced and not be equal for i, ix, q, qx. if symmetry and full band- width is required, the lowpass pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the i/q outputs can be increased further by using a resistor between pins 3, 4, 9 and 10. these resistors shunt the internal loads of ri ~ 5.4 k ? . the decrease in gain here has to be considered. 6. the internal current of the output emitter followers is 0.6 ma. this redu ces the undistorted output voltage swing at a 50 ? load to approximately 30 mv. for low signal distortion the load impedance should be ri 5 k ? . 7. referred to the level of the output vector 8. the low-gain status is achieved with an open or high- ohmic pin 11. a recommended application circuit for switching between high and low gain status is shown in figure 6-1 . i 2 q 2 +
7 4653d?cell?11/05 u2794b figure 6-1. test circuit * optional for single-ended tests (notice 3 db bandwidth of ad620) t1, t2 = transmission line z o = 50 ? . if no gc function is required, connect pin 11 to gnd. for high and low gain status gc is to be switched to gnd respectively to v s . figure 6-2. i and q phase for f rf > f lo . for f rf < f lo the phase is inverted. -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 5 10 15 20 25 30 time (arbitrary units) i/q output normalized qi
8 4653d?cell?11/05 u2794b figure 6-3. typical vswr frequency response of the lo input figure 6-4. noise figure versus lo frequency; o: value at 950 mhz with rf input matching with t3 figure 6-5. typical suitable lo power range versus frequency 50 250 450 650 850 1 2 3 4 5 6 v s w r lo frequency ( mhz ) 1050 8 10 12 14 16 18 0 200 400 600 800 1000 lo frequency (mhz) nf (db) -50 -40 -30 -20 -10 0 30 40 50 60 70 80 90 lo frequency (mhz) plo (dbm) p lomax p lomin
9 4653d?cell?11/05 u2794b figure 6-6. gain versus lo frequency; x: value at 950 mhz with rf input matching with t3 figure 6-7. typical output signal versus lo frequency for p rf = ?15 dbm and plo = ? 15 dbm figure 6-8. typical suitable lo power range versus frequency 10 14 18 22 26 30 0 200 400 600 800 1000 lo frequency (mhz) gain (db) 800 900 1000 1100 1200 1300 1400 1500 1600 0 200 400 600 800 1000 lo frequency (mhz) vi/qout (mvpp) -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 lo frequency (mhz) plo (dbm)
10 4653d?cell?11/05 u2794b figure 6-9. typical output voltage (single ended) versus p rf at t amb = 25c and plo = ? 15 dbm figure 6-10. typical s11 fre quency response a: lo input, lo frequency from 100 mhz to 1100 mhz, marker: 950 mhz b: rf input, rf frequency from 100 mhz to 1100 mhz, marker: 950 mhz c: i/q outputs, baseband frequency from 5 mhz to 55 mhz, marker: 25 mhz 0 200 400 600 800 1000 1200 1400 1600 1800 -40 -35 -30 -25 -20 -15 -10 p rf (dbm) vi/qout (mvpp) -0.2j -0.5j -j -2j -5j 0 0.2j 0.5j j 2j 5j 0.2 0.5 1 2 5 1 a b c b a c
11 4653d?cell?11/05 u2794b figure 6-11. evaluation board layout figure 6-12. evaluation board
12 4653d?cell?11/05 u2794b 6.1 external components 6.2 calibration part 6.3 conversion to single ended output (see datasheet of ad620) cucc 100 nf crfx 1 nf clo 100 pf cnlo 1 nf crf 100 pf cii, cqq optional extern al lowpass filters t3 transmission line for rf-input matching, to connect optionally ci, cix optional for ac-coupling at cq, cqx baseband outputs cpdn 100 pf not connected cgc 100 pf cpc 100 pf not connected cnpc 100 pf not connected gsw gain switch co, cs, cl 100 pf rl 50 ? op1, op2 ad620 rg1, rg2 prog. gain, see datasheet, for 5.6 k ? a gain of 1 at 50 ? is achieved together with rd1 and rd2. rd1, rd2 450 ? cs1, cs2 100 nf cs3, cs4 100 nf
13 4653d?cell?11/05 u2794b 7. description of the evaluation board board material: epoxy; r = 4.8, thickness = 0.5 mm, transmission lines: z o = 50 ? the board offers the following functions: test circuit for the u2794b: ? the supply voltage and the control inputs gc, pc and pu are connected via a plug strip. the control input voltages can be generated via external potentiometers; then the inputs should be ac-grounded (time requirements in burst mode for power up have to be considered). ? the outputs i, ix, q, qx are dc coupled via an plug strip or can be ac-connected via smb plugs for high frequency tests e.g. noise figure or s-parameter measurement. the pins ii, iix, qq, qqx allow user-definable filtering with 2 external capacitors cii, cqq. ? the offsets of both channels can be adjusted with two potentiometers or resistors. ? the lo- and the rf-inputs are ac-coupled and connected via smb plugs. if transmission line t3 is connected to the rf-input and ac-grounded at the other end, gain and noise performance can be improved (input matching to 50 ? ). ? the complementary rf-input is ac-coupled to gnd (crfx = 1 nf), the same appears to the complementary lo input (cnlo = 1 nf). a calibration part which allows to calibrate an s-parameter analyzer directly to the in- and output- signal ports of the u2794b. for single-ended measurements at the demodulator outputs, two ops (e.g., ad620 or other) can be configured with programmable gain; together with an output-divider network rd = 450 ? to rl = 50 ? , direct measurements with 50 ? load impedances are possible at frequencies t < 100 khz.
14 4653d?cell?11/05 u2794b 9. package information 8. ordering information extended type number package remarks u2794b-nfsh sso20 tube, moq 830 pcs, pb-free u2794b-nfsg3h sso20 taped and reeled, moq 4000 pcs, pb-free technical drawings according to din specifications package sso20 dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 110
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